1. Field of the Invention
The present invention relates to a fundamental cell that constitutes a basic unit in the layout of a semiconductor integrated circuit device, a semiconductor integrated circuit device which uses such fundamental cells, a wiring method as well as a wiring apparatus thereof, and more particularly to a fundamental cell that may be used in a semiconductor integrated circuit device of the gate array type and standard array type, a semiconductor integrated circuit device that uses such fundamental cells, and a wiring method as well as wiring apparatus thereof.
2. Description of the Related Art
A semiconductor integrated circuit device of the gate array type and standard cell type is used so far, in which functional circuit blocks constituted of fundamental cells in a matrix structure are arranged. FIG. 12 shows a typical example of a fundamental cell 100. The fundamental cell 100 has therein a power supply voltage wiring VDD and ground potential wiring VSS, or so-called the power rails VDD and VSS in order to supply the power supply voltage VDD and grand potential VSS respectively to the fundamental cell 100. connection terminals 2 and 3 are used for biasing N-type well region of a PMOS (P-channel metal oxide semiconductor) transistor and P-type well region of an NMOS (N-channel metal oxide semiconductor) transistor to the power supply voltage VDD and the ground potential VSS, respectively.
When the power rails VDD and VSS or the connection terminals 2 and 3 are placed fixedly in the fundamental cell 100, if the fundamental cells 100 are arranged in a matrix (see also FIG. 13 and FIG. 14), the power rails VDD and VSS or the connection terminals 2 and 3 will be placed in a predetermined wiring track. Thus the power rails VDD and VSS have been designed to include the connection terminals 2 and 3 between fundamental cells 100 so as to coincide with the wiring track specification of the fundamental cell 100 in the row direction of the fundamental cells 100 (direction lateral to the fundamental cells 100)in each fundamental cell 100. The power rails VDD and VSS will be made at the same time as the fundamental cells 100 are arranged in a matrix so as to constitute a functional circuit block 200. As shown in FIG. 14, the power rails VDD and VSS will be wired in parallel to the wiring track along with the row direction of the fundamental cells 100 (lateral to the fundamental cells 100) when the fundamental cells 100 are placed. The power rails VDD and VSS are, in general, so important wirings for operating the circuit that the wirings are formed with metal wiring layer M1, the lowest layer.
However, in the fundamental cell 100 in accordance with the Related Art as have been described above, the wirings of the power rails VDD and VSS will be completed at the same time as the fundamental cells 100 are arranged in a matrix so as to form a functional circuit block, however, there will be problems that the wiring direction, width of wirings, the wiring layer of the power rails VDD and VSS cannot be moved or changed from the lowest metal wiring layer M1.
Now referring to FIG. 13, there is shown a layout example of four fundamental cells 100A, 100B, 100C, and 100D in a matrix of 2 by 2 grid to form a functional circuit block 200 as shown by the operating circuit in FIG. 3. As can be appreciated clearly from the figure, the power rails VDD and VSS are formed in the lowest metal wiring layer M1, in a predetermined width of wirings along with the wiring track extending in the row direction from the fundamental cell 100A to the fundamental cell 100D (lateral direction extending from the fundamental cell 100A to the fundamental cell 100D). In other words, the power rails VDD and VSS are wired and formed in the lowest metal wiring layer M1 between the outputs of the fundamental cell 100C forming a NOR1 and the fundamental cell 100D forming a NOR2, and the given gates of the fundamental cells 100A and 100B forming NAND1 having these outputs as input. In the semiconductor integrated circuit devices of the gate array type and standard cell type, in general, upper metal wiring layers are used for wiring between functional circuit blocks, and the signal wirings within a functional block are made by using the lowest metal wiring layer M1 together with the power rails VDD and VSS. The connection between NOR1 and NAND1 and the connection between NOR2 and NAND1 need to bridge over the power rails VDD and VSS formed in the lowest metal wiring layer M1, by routing through the metal wiring layer M2 through VIA 101A and 101C, and through VIA 101B and 101D, respectively. When the functional circuit block is much larger, the wirings need to bridge over the power rails VDD and VSS more often to spoil the degree of freedom of metal wirings and to complicate the structure of metal wirings. In addition, the number of wirings in the upper metal wiring layer M2 will become numerous to narrow the wiring space in the upper metal wiring layer M2. When wiring other signal lines using the same wiring layer, while having the power rails VDD and VSS fixed to fundamental cells 100, the number of wiring tracks is required to increase as much as needed to finally increase the cell height of fundamental cell 100. This may cause another problem of disturbance in the integration of semiconductor integrated circuit device.
Furthermore, as shown in FIG. 14, since the wiring direction, wiring width, and wiring layer of power rails VDD and VSS are fixed, the wiring scheme of power rails VDD and VSS may not be allowed to change so as to conform to the circuit specification of a functional circuit block 300 having fundamental cells 100 (M, N) arranged in a matrix grid (where M and N are integer equal to or more than 1). In other words, there may be cases in which a capability of delivering sufficient power supply for performing desired operation in the functional circuit blocks that operates at a very increased speed or that drives a large load cannot be ensured. In addition, there may be cases in which the wiring pitch is narrower than required to have the potential of delivering power to the loaded functional circuit blocks that consume small current, so that it may interfere higher integration.
In FIG. 14, since the wiring direction, wiring width, and wiring layer of power rails VDD and VSS for fundamental cells 100 (M, N) are fixed, the wiring will be also fixed in the functional circuit block 300 of fundamental cells 100 (M, N) arranged accordingly. When forming a semiconductor integrated circuit device of the gate array type or standard cell type by combining such functional circuit blocks 300, the wiring direction, wiring width, and wiring layer of power rails VDD and VSS in the functional circuit blocks 300 will be inherently fixed. Thus, there may be cases in which functional circuit blocks 300 cannot be arranged so as to conform to the wiring of power rails VDD and VSS around the functional circuit blocks 300, resulting in a problem that a further integration in a semiconductor integrated circuit device of the gate array type and standard cell type will be interfered.